Thesis: Induced Hierarchical
Verification of Asynchronous Circuits Using a Partial Order Technique
The
Design and Verification of a Low-Control-Overhead Asynchronous Differential
Equation Solver, K. Y. Yun, P. A. Beerel, V. Vakilotojar, A. Dooply,
and J. Arceo. In IEEE Transactions on VLSI, Dec. 1998.
Hiding
Memory Elements in Induced Hierarchical Verification of Speed-Independent
Circuits, V. Vakilotojar and P. A. Beerel, IWLS-98, June 1998.
Also presented in SRC
TECHCON'98, Sept. 98.
RTL
Verification of Timed Asynchronous and Heterogeneous Systems using Symbolic
Model Checking, V. Vakilotojar and P. A. Beerel, INTEGRATION, The
VLSI Journal, December 1997.
The
Design and Verification of a Low-Control-Overhead Asynchronous Differential
Equation Solver, K. Y. Yun, P. A. Beerel, V. Vakilotojar, A. Dooply,
and J. Arceo. ASYNC-97, April 1997.
RTL
Verification of Timed Asynchronous and Heterogeneous Systems using Symbolic
Model Checking, V. Vakilotojar and P. A. Beerel, ASPDAC-97, January
1997.
A
Low-Control-Overhead Asynchronous Differential Equation Solver,
K. Y. Yun, P. A. Beerel, V. Vakilotojar, A. Dooply, and J. Arceo, ESSCIRC-96,
pp. 352-255. September, 1996.
