Wei-Chun Chou Ph.D., EE-Systems, USC

Current Status:

• Senior Application Consultant in Synopsys, Mountain View, CA, since Aug 2004

Education:

• B.S. in Nuclear Engineering, National Tsing Hua University, Hsinchu, Taiwan, 1985.
• M.S. in Electrical Engineering, National Taiwan University, Taipei, Taiwan, 1992.
• Ph.D. in Electrical Engineering, University of Southern California, Los Angeles, California, USA, 1999.

Professional Experience:

• Senior Application Consultant, Synopsys, Mountain View, CA (8/2004-present)
  1. Specialized in supporting P&R optimization software (Astro, JupiterXT, Physical Compiler, IC Compiler)
• CAD engineer, Manager Paul Yip, Sun Microsystems, Sunnyvale, CA (8/1999-6/2004)
  1. Responsible for the control block CAD methodology for UltraSPARC microprocessor design. The methodology includes both frontend logic synthesis and backend physical place & route synthesis.
  2. Focus on solving signal intergrity issues, such as crossstalk noise, in the control block flow.
  3. Develop a transistor-sizing tool for UltraSPARC.
• Research assistant, Advisor Peter Beerel, USC, LA, CA (7/1996-8/1999)
  1. Studied technology mapping for optimizing average-case performance in asyn chronous circuits.
  2. Studied high-level synthesis for asynchronous circuits.
  3. Implemented a technology mapper in C language and Perl (about 13000 lines) within Berkeley SIS package on both Sun-Solaris workstation and Linux-PC systems.
• Co-op student, Supervisor Shai Rotem, Intel Corporation, Hillsboro, OR (1/1996-7/1996)
  1. Worked on Asynchronous Instruction Length Decoder Project.
  2. Investigated GHz circuit synthesis technique for deep submicron technology.
  3. Studied aggressive self-timed technique for high-speed circuit design.

Ph.D. Thesis:

• Optimizing Average-Case Performance in the Technology Mapping of Asynchronous Circuits. (main.ps)

Publications:

1. Wei-Chun Chou and Peter A. Beerel, "Average-Case Technology Mapping of Asynchronous Burst-Mode Circuits," IEEE Transaction on Computer-Aided Design, Oct. 1999. (tcad-final.ps)
2. Wei-Chun Chou, Peter A. Beerel, Ran Ginosar, Rakefet Kol, Chris J. Myers, Shai Rotem, Kenneth Stevens, Kenneth Y. Yun, "Average-Case Optimized Technology Mapping of One-Hot Domino Circuits," Proceedings of Async '98, pp. 80-91, Mar. 1998. (async98.ps)
3. Peter A. Beerel, Kenneth Y. Yun, Wei-Chun Chou, "Optimizing Average-Case Delay in Technology Mapping of Burst-mode Circuits," Proceedings of Async '96, pp. 244-260, Mar. 1996. (async96.ps)
4. Peter A. Beerel, Kenneth Y. Yun, Wei-Chun Chou, "A Heuristic Covering Technique for Optimizing Average-Case Delay in the Technology Mapping of Asynchronous Burst-Mode Circuits," Euro-DAC '96. (eurodac96.ps)
5. Wei-Chun Chou, Tai-Ming Parng, Feipei Lai, Feng-Ho Kuo, and Te-Son Kuo, "Design and Implementation of 4X4 Crossbar Interconnection Network Board for Large Scale Multiprocessor System - Azalea," Proceedings of the National Science Council, Taiwan, pp. 429-438, Sept. 1994.

Average-Case Optimized Technology Mapper (AVEmap)