Overview
Digital system designers
usually use Hardware Descriptive Languages to design
and model their circuits. These languages are used
to describe the circuit behavior at several levels
of abstraction. Verilog and VHDL have been the most
popular HDLs.
Asynchronous circuit designers,
however, often use some form of
communicating sequential processes (CSP) to
model the intended architectural behavior, because
it has two essential features: channel-based
communication and fine grained concurrency. The
former makes data exchange between modules abstract
actions. The latter allows one to define nested
sequential and concurrent threads in a model. Thus,
a practical Hardware Description Language (HDL) for
high-level asynchronous design should implement the
above two constructs. Furthermore, similar to many
standard HDLs, the following features are highly
desired:
-
Support for various levels
of abstraction
-
Support for synchronous
circuits
-
Support for timing
-
Using available supporting
CAD tools
-
A standard syntax
VerilogCSP is a library of macros
to support CSP Send/Receive channels in standard
Verilog, so that it adds the above mentioned
features of CSP language to a standard HDL like
Verilog. Using VerilogCSP one can describe nonlinear
pipelines and high-level channel timing properties,
such as forward and backward latencies, minimum
cycle time, and slack, at a very high level, and
measure the pipeline performance.
For a detailed explanation of
VerilogCSP, please refer to the following paper:
"High Level Modeling of
Channel-Based Asynchronous Circuits Using Verilog",
Arash Saifhashemi and Peter A. Beerel, CPA2005
How does VerilogCSP look
like?
The
following example shows how the process Sender sends
data to the process Consumer:
|
module
Sender(out);
`OUTPORT(out,8);
`USES_CHANNEL
reg [7:0]d;
always
begin
//Produce
d
`SEND(out,d)
end
endmodule |
module Receiver(in);
`INPORT(in,8);
`USES_CHANNEL
reg [7:0]d;
always
begin
`RECEIVE(in,d)
//Consume d
end
endmodule |
|
module
top;
`CHANNEL (ch,8)
Sender p(ch);
Receiver c(ch);
endmodule |
VerilogCSP Macros
VerilogCSP
adds a few macros to the standard Verilog. The
macros are defined in a separate file.
The macros
are as follows:
|
Macro |
Description |
|
USES_CHANNEL |
This macro shall be
used in variable declaration area of
always blocks of any module that uses
VerilogCSP macros |
|
INPORT(p,l) |
Defines an input
port p of size l+2. The extra two least
significant bits are uses by macros for
handshaking. |
|
OUTPORT(p,l) |
Defines an output
port p of size l+2. The extra two least
significant bits are uses by macros for
handshaking. |
|
CHANNEL(c,l) |
Defines a channel c
of size l+2. The extra two least
significant bits are uses by macros for
handshaking.
Channels should be
used to connect two modules that perform
communication actions. |
|
SEND(p,
v) |
Sends value v on
port p |
|
RECEIVE(p,
v) |
Receives the value
of port p and copies it into variable v |
|
SEND_SYNC(p) |
Sends a sync
message on port p |
|
RECEIVE_SYNC(p) |
Receives a sync
message from port p |
|
SEND_P1(p,v) |
Split SEND, part 1 |
|
SEND_P2(p,v) |
Split SEND, part 2 |
|
RECEIVE_P1(p,v) |
Split RECEIVE, part
1 |
|
RECEIVE_P2(p,v) |
Split RECEIVE, part
2 |
|
SEND_SYNC_P1(p,v) |
Split SEND_SYNC,
part 1 |
|
SEND_SYNC_P2(p,v) |
Split SEND_SYNC,
part 2 |
|
RECEIVE_SYNC_P1(p,v) |
Split RECEIVE_SYNC,
part 1 |
|
RECEIVE_SYNC_P2(p,v) |
Split RECEIVE_SYNC,
part 2 |
|
PROBE_IN(p) |
Probes input port p
and returns true if the mutual process
on the port connected to p is trying to
SEND. If the value of probe is true, it
is safe to perform a RECEIVE action on
p. |
|
PROBE_OUT(p) |
Probes output port
p and returns true if the mutual process
on the port connected to p is trying to
RECEIVE. If the value of probe is true,
it is safe to perform a SEND action on
p. |
Notice that the least
significant two bits on ports are used for
handshaking. The user, however, does not need to be
concerned about these two bits. The SEND and RECEIVE
macros take care of the necessary data shift while
transferring data from the port to the variable. The
example at the end of this page shows how these
macros should be used.
VerilogCSP.v Macro Definition
File
In order to
use VerilogCSP macros, VerilogCSP.v file should be
included at the beginning of the files which contain
modules using CSP channels.
Download VerilogCSP.v from
here
Debugging VerilogCSP with Modelsim Virtual Functions
We have used Modelsim advanced
debugging features to simplify debugging VerilogCSP
designs. In particular, the Virtual Functions enable
us to display the status of VerilogCSP channels in
the waveform viewer. We have zipped the script files
as well as PPT instructions
here. For more
information on advanced debugging features,
including virtual functions, please refer to the
Modelsim Command Reference Manual.
Examples
You can download some examples
using VerilogCSP macros from
here.
Feedbacks:
Please send feedbacks to
saifhash[at]usc[dot]edu
