Proteus

Proteus Flow

 

Full-custom asynchronous design has for some time now offered a means of achieving low-latency and high-throughput. However, its application has been somewhat limited by a labor-intensive design cycle, involving many levels of manual circuit decomposition and physical design that require highly-specialized designers. Proteus is a new asynchronous ASIC CAD flow that enables the automatic synthesis, sizing, and physical design of high-level specifications in communicating sequential processes to GHz silicon, greatly reducing design time and enabling far wider use of asynchronous design.

The flow’s target is 2-3X higher performance than typically possible for synchronous counterparts, namely 1.1GHz in TSMC 65nm. It is based on a proprietary cell library of domino logic and asynchronous control cells, small collections of gates sized, layed out, and characterized as single library cells,  designed to implement robust high-performance pipelined circuits [4]. The Proteus flow leverages both synchronous synthesis and place-and-route tools and supports as a starting point both legacy RTL as well as System Verilog with custom-build interfaces for modeling asynchronous communication primitives akin to communicating sequential processes (CSP).

 

More details of the FloW can be found in the following articles.

  1. P. A. Beerel, G. D. Dimou, and A. M. Lines, "Proteus: An ASIC Flow for GHz Asynchronous Designs," IEEE Design & Test of Computers, vol. 28, pp. 36-51, 2011.
  2. A. Saifhashemi, P. A. Beerel. “SystemVerilogCSP: Modeling Digital Asynchronous Circuits Using SystemVerilog Interfaces”, Proceedings of Communicating Process Architectures - WoTUG-33, June 2011.
  3. Georgios D. Dimou, Peter A. Beerel, Andrew Lines: Performance-Driven Clustering of Asynchronous Circuits. PATMOS 2011, pp. 92-101, Sept.  2011.
  4. P. Golani and P. A. Beerel, “Area-Efficient Multi-Level Single-Track Pipeline Template”, DATE 2011, March 2011.
  5. See more sliders here
  6. A. Saifhashemi and P. A. Beerel, "Observability Conditions and Automatic Operand-Isolation in High-Throughput Asynchronous Pipelines", PATMOS 2012 viagra without prescription

Asynchronous Design in the News

ASYNC 2016 will be held May 8-11 in Porto Alegre Brazil. Peter Beerel is PC-Co-Chair.

Peter Beerel gives Keynote Lecture "Blade - A Path towards Average-Case Silion via Bundled-Data Resilient Design" at Chip-In 2015 in Bahia, Brazil. (Slides are available here.) 

Group co-authors 3 paper at ASYNC 2016 and 5 papers at ASYNC 2014. Merhdad wins 2014 Best Paper Award! See publications for details.