USC Asynchronous CAD/VLSI Group

Driven by overwhelming design-time constraints, synchronous design styles supported by mature CAD design tools and a largely automated flow dominate the semi-conductor market place. As we march towards the end of Moore’s law and beyond, however, the reliance on a global clock becomes increasingly difficult, yielding far-from-optimal solutions. Alternatives, such as asynchronous design have become increasingly practical but overcoming the momentum of the synchronous paradigm is challenging. In particular, asynchronous circuits are particularly attractive for power-constrained applications because asynchronous blocks that receive no tokens can remain idle, consuming no dynamic power and can be resilient to high process voltage and temperature (PVT) variations. However, the lack of a complete ASIC flow for asynchronous design has prevented wide-spread adoption.

One start-up that addressed this challenge was TimeLess Design Automation, based upon USC research and co-founded by Professor Peter A. Beerel and his former PhD student Georgios Dimou. TimeLess developed a complete ASIC flow, called Proteus, for asynchronous circuits and was bought by Fulcrum Microsystems in 2010, which was later acquired by Intel in 2011.

Funded by both Qualcomm and NSF, the USC Asynchronous CAD/VLSI group now investigates next generation asynchronous circuits and CAD flows, including research topics in design, analysis, synthesis, test, and verification. It is located within the Ming Hsieh Department of Electrical Engineering  of the University of Southern California.




Asynchronous Design in the News

ASYNC 2016 will be held May 8-11 in Porto Alegre Brazil. Peter Beerel is PC-Co-Chair.

Peter Beerel gives Keynote Lecture "Blade - A Path towards Average-Case Silion via Bundled-Data Resilient Design" at Chip-In 2015 in Bahia, Brazil. (Slides are available here.) 

Group co-authors 3 paper at ASYNC 2016 and 5 papers at ASYNC 2014. Merhdad wins 2014 Best Paper Award! See publications for details.