Low-Power, High-Performance and Resilient Designs
- Ramy N. Tadros, Nihar Dasari, and Peter. A. Beerel, “'Ultra-Low Power PTL-based Delay Line Design for Sub-threshold Application,” Accepted to Electronic Letters , Oct 2016.
- Ramy N. Tadros*, Weizhe Hua*, Matheus T. Moreira, Ney L. V. Calazans, and Peter A. Beerel. A Low Power, Low Area Error Detecting Latch for Resilient Architectures in 28nm FDSOI”, IEEE Transactions on Circuits and Systems II, vol. 63, no. 9, Sept. 2016.
- Weizhu Hua, Ramy N. Tadros, and Peter A. Beerel. A 2ps Resolution, Fine-Grained Delay Element in 28nm FDSOI”, Electronic Letters, vol. 51, no. 23, pp. 1848 – 1850, 2015.
- Peter A. Beerel and Ney L.V. Calazans: A Path Towards Average-Case Silicon via Asynchronous Resilient Bundled-data Design. 22nd European Conference on Circuit Theory and Design (ECCTD'15), (Invited) Aug. 2015
- Dylan Hand, Matheus T. Moreira, Hsin-Ho Huang, Danlei Chen, Fredericko Butzke, Zhichao Li, Matheus Gibiluka, Melvin Breuer, Ney. L.V. Calazans, Peter A. Beerel: Blade - A Timing Violation Resilient Asynchronous Template, ASYNC 2015, May 2015.
- Ajay Singhvi, Matheus T. Moreira, Ramy N. Tadros, Peter A. Beerel, Ney L.V. Calazans: A Fine-Grained, Uniform, Energy-Efficient Delay Element for FD-SOI Technologies, International Symposium on VLSI (ISVLSI'15), July 2015.
- Matheus T. Moreira, Dylan Hand, Peter A. Beerel, Ney L.V. Calazans: TDTB error detecting latches: Timing violation sensitivity analysis and optimization. ISQED 2015: 379-383.
- Guiherme Heck, Leandro Heck, Ajay Singhvi, Matheus T. Moreira, Peter A. Beerel, Ney L.V. Calazans, Design and Analysis of Delay Elements for 2-Phase Bundled-Data Asynchronous Circuits, VLSI Design, Jan. 2015.
- Mike Davies, Andrew Lines, Jon Dama, Alain Gravel, Robert Southworth, Georgios D. Dimou, Peter A. Beerel: A 72-Port 10G Ethernet Switch/Router Using Quasi-Delay-Insensitive Asynchronous Design. ASYNC 2014: 103-104, May 2014.
Power, Performance, and Timing Analysis and Optimization
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Dylan Hand, Hsin-Ho Huang, Benmao Cheng, Yang Zhang, Matheus T. Moreira, Melvin A. Breuer, Ney L. V. Calazans, Peter A. Beerel: Performance Optimization and Analysis of Blade Designs under Delay Variability. ASYNC 2015: 61-68, May 2015.
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Arash Saifhashemi, Hsin-Ho Huang, Peter A. Beerel: Reconditioning: Automatic Power Optimization of QDI Circuits. ASYNC 2014: 77-84, May 2014.
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Arash Saifhashemi, Dylan Hand, Peter A. Beerel, William Koven, Hong Wang: Performance and Area Optimization of a Bundled-Data Intel Processor through Resynthesis. ASYNC 2014: 110-111, May 2014.
- Mehrdad Najibi, Peter A. Beerel: Integrated Fanout Optimization and Slack Matching of Asynchronous Circuits. ASYNC 2014: 69-76, May 2014. (Best Paper Award Winner)
- Slack Matching Mode-Based Asynchronous Circuits for Average-case Performance, Mehrdad Najibi and Peter A. Beerel, ICCAD 2013, Nov 18th-21st, 2013,
- Deriving Performance Bounds for Conditional Asynchronous Circuits using Linear Programming, Mehrdad Najibi and Peter A. Beerel, 19th IEEE Symposium on Asynchronous Circuits ASYNC, Santa Monica, CA, May 19-22, 2013. (Best Paper Award Nominee)
- Guowei Zhang, Peter A. Beerel: Stochastic analysis of Bubble Razor. DATE 2014: 1-6., March 2014.
- Performance Bounds of Asynchronous Circuits with Mode-Based Conditional Behavior, Mehrdad Najibi and Peter A. Beerel, 18th IEEE Symposium on Asynchronous Circuits ASYNC, Copenhagen of Denmark, May 7-11, 2012.
- Energy and Performance Models for Synchronous and Asynchronous Communication. Kenneth S. Stevens, Pankaj Golani, Peter A. Beerel. 2011, IEEE Trans. VLSI Syst., pp.369-382.
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Timing Verification of GasP Asynchronous Circuits: Predicted Delay Variations Observed by Experiment, Prasad Joshi, Peter A. Beerel, Marly Roncken, and Ivan Sutherland, In D. Dams, U. Hannemann, M. Steffen (Eds.) Willem-Paul de Roever Festschrift, LNCS 5930, pages 260-276. Springer-Verlag Berlin Heidelberg, 2010.
Proteus and other Async Synthesis
- Georgios D. Dimou, Peter A. Beerel, Andrew Lines: Performance-Driven Clustering of Asynchronous Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 33(2): 197-209, 2014.
- A. Saifhashemi and P. A. Beerel, "Observability Conditions and Automatic Operand-Isolation in High-Throughput Asynchronous Pipelines", PATMOS 2012.
- P. A. Beerel, G. D. Dimou, and A. M. Lines, "Proteus: An ASIC Flow for GHz Asynchronous Designs," IEEE Design & Test of Computers, vol. 28, pp. 36-51, 2011.
- A. Saifhashemi, P. A. Beerel. “SystemVerilogCSP: Modeling Digital Asynchronous Circuits Using SystemVerilog Interfaces”, Proceedings of Communicating Process Architectures - WoTUG-33, June 2011.
- Georgios D. Dimou, Peter A. Beerel, Andrew Lines: Performance-Driven Clustering of Asynchronous Circuits. PATMOS 2011, pp. 92-101, Sept. 2011.
- P. Golani and P. A. Beerel, “Area-Efficient Multi-Level Single-Track Pipeline Template”, DATE 2011, March 2011.
Testability
- Y. Zhang, L. S. Heck, M. T. Moreira, D. Zar, M. A. Breuer, N. L. V. Calazans, P. A. Beerel. “Testable MUTEX Design,” IEEE Transactions on Circuits and Systems I , vol. 63, No. 8, Aug. 2016.
- Y. Zhang, L. S. Heck, M. T. Moreira, D. Zar, M. A. Breuer, N. L. V. Calazans, P. A. Beerel: Design and Analysis of Testable Mutual Exclusion Elements. ASYNC 2015: 124-131
- P. A. Beerel and T. H.-Y. Meng, Semi-modularity and Testability of Speed-Independent Circuits, Integration, The VLSI Journal, pp. 301-322. Sep. 1992.
Formal Verification
- A. Saifhashemi,; H.-H. Huang; P. Bhalerao, P.A. Beerel, "Logical equivalence checking of asynchronous circuits using commercial tools," in Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015 , vol., no., pp.1563-1566, 9-13 March 2015.
- Relative Timing Based Verification of Timed Circuits and Systems, H. Kim, P.A. Beerel and K.S. Stevens. ASYNC'02, April 2002.
- Relative Timing Based Verification of Timed Circuits and Systems, H. Kim and P.A. Beerel. IWLS'99, June 1999. (PowerPoint presentation slides).
BDDs
- Sibling-substitution-based BDD minimization using don't cares, Y. Hong, P. A. Beerel, J.R. Burch and K.L. McMillan, IEEE Transaction on CAD, Vol: 19 Issue: 1, Jan. 2000.
Theses
- Power optimization of asynchronous pipelines using conditioning and reconditioning based on a three-valued logic model, Arash Saifhashemi, Ph.D. Thesis, University of Southern California, December 2012.
- Theory, Implementations, and Applications, of Single-Track Designs, P. Pankaj, Ph.D. Thesis, University of Southern California, May 2010.
- Clustering and Fanout Optimization of Asynchronous Circuits, G. Dimou, Ph.D. Thesis, University of Southern California, May 2009.
- Static Timing Analysis of GasP, P. Joshi, MS. Thesis, University of Southern California, Dec 2008.
- Library Characterization and Static Timing Analysis of Asynchronous Circuits, M. Prakash, MS. Thesis, University of Southern California, Dec 2007.
- Single-track Asynchronous Pipeline Template, M. Ferretti, Ph.D. Thesis, University of Southern California, Aug, 2004.
- Template-Based Asynchronous Circuit Design, R.O. Ozdag, Ph.D. Thesis, University of Southern California, Nov, 2003.
Patents
- Mallika Prakash, Peter A. Beerel. “Static timing analysis of template-based asynchronous circuits,” United States Patent No. 8,972,915, March 3, 2015.
- Georgios Dimou, Peter A. Beerel, Andrew Lines. "Multi-level domino, bundled data, and mixed templates," July 23, 2013, United States Patent No. 8,495,543.
- Georgios Dimou, Peter A. Beerel, Andrew Lines. "Clustering and fanout optimizations of asynchronous circuits," May 21, 2013. United States Patent No. 8,448,105.
- Ken Shiring, Peter A. Beerel, Andrew Lines, and Arash Saifhashemi. "Power aware asynchronous circuits", Dec 27, 2011, United States Patent No. 8,086,975.
- Peter Beerel, Andrew Lines, Michael Davies. "Logic synthesis of multi-level domino asynchronous pipelines," Nov 1, 2011: US Patent No. 8,051,396.
- Peter A. Beerel, Keith M. Chugg, Georgios D. Dimou, Phunsak Thiennviboon. "Reduced-latency soft-input/soft-output module", March 27, 2007. United States Patent No. 7,197,691.