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USC Asynchronous
CAD/VLSI group is investigating Asynchronous and Mixed
Synchronous-Asynchronous System Design, Analysis, Synthesis, and
Verification. It is located within
Electrical Engineering of the
University of Southern California.
Our goal is to
develop an application-specific integrated-circuit (ASIC) synthesis
and place and route flow for high-speed asynchronous designs using
standard-cell libraries.
We
design, fabricate, and test chips to demonstrate the advantages of
the developed flow and circuits. This year we are working on a 0.18
micron technology test chip implementing a turbo decoder. This chip
will be submitted to the SRC/SIA design contest
Our
Group, in conjunction with Columbia University, announced the
introduction of an asynchronous standard cell library based on the PCHB (Pre-Charged Half Buffer) and the STFB (Single Track Full
Buffer) templates. All the cells/gates in both of the libraries have
functional, schematic, layout and symbol views that support Cadence DFII files for automatic place and route using Silicon Ensemble.
Both detailed documentation and the tarred GDS libraries accessible
though the
MOSIS Education Prograum Cooperative IP Program which enables
downloading of the GDS and documentation via a
secure
document access web page. This research has been supported by an
NSF ITR grant #0086036.
We and
Professor Steven
Nowicks's Group
at Columbia University, have developed several new circuit families
for high-speed asynchronous design. Moreover, we are actively
pursuing a full CAD flow for these designs that includes synthesis
and place and route.
Asynchronous
Design in the News
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