Publications

Thesis:

• Single-track Asynchronous Pipeline Template, M. Ferretti, Ph.D. Thesis, University of Southern California, Aug, 2004.
• Template-Based Asynchronous Circuit Design, R.O. Ozdag, Ph.D. Thesis, University of Southern California, Nov, 2003.
• Low-Power Circuit Techniques for Battery-Powered DSP Applications, J.S. Moon, Ph.D. Thesis, University of Southern California, June, 2003.
• Pipeline Optimization for Asynchronous Circuits: Complexity Analysis and an Efficient Optimal Algorithms, S. Kim, Ph.D. Thesis, University of Southern California, May, 2003.
• Induced Hierarchical Verification of Asynchronous Circuits Using a Partial Order Technique, V. Vakilotojar, Ph.D. Thesis, University of Southern California, August, 1999.
• Performance Analysis of Asynchronous Circuits and Systems, A. Xie, Ph.D. Thesis, University of Southern California, August, 1999.
• Optimizing Average-Case Performance in the Technology Mapping of Asynchronous Circuits , W.-C. Chou, Ph.D. Thesis, University of Southern California, August, 1999.
• BDD Minimization using Don't Cares for Formal Verification and Logic Syntheis, Y. Hong, Ph.D. Thesis, University of Southern California, August, 1998.
• CAD Tools for the Synthesis, Verification, and T estability of Robust Asynchronous Circuits, P. A. Beerel, Ph.D. Thesis, Stanford University, August, 1994.

Patents:

• Peter A. Beerel, Keith M. Chugg, Georgios D. Dimou, Phunsak Thiennviboon. "Reduced-latency soft-input/soft-output module" March 27, 2007. United States Patent No. 7,197,691.
• Frederik Eaton and Peter A. Beerel. "Optimization of cell subtypes in a hierarchical design flow" February 8, 2005. United States Patent No. 6,854,096.
• Peter A. Beerel, Andrew Lines, and Qing Wu. "Methods and apparatus for facilitating physical synthesis of an integrated circuit design" August 31, 2004. United States Patent No. 6,785,875.
• Peter A.Beerel; Keith M. Chugg; Recep Ozdag; Sunan Tugsinavisut; Sushil K. Singh; Phunsak Thiennviboon. "Sequential decoder for decoding of convolutional codes" February 10, 2004. United States Patent No. 6,690,752.
• Aiguo Xie and Peter A. Beerel. "Formal Verification of a Logic Design Using Implicit Enumeration of Strongly Connected Components.'' February 25th, 2003. United States Patent No. 6,536,551.
• Ken Stevens, Shai Rotem, Ran Ginosar, Peter Beerel, Ken Yun, Chris Myers, Rakefet Kol. "Apparatus and Method for Parallel Processing and Self-Timed Serial Marking of Variable Length Instructions''. November 2, 1999. United States Patent No. 5,978,899.
• Ken Stevens, Shai Rotem, Ran Ginosar, Peter Beerel, Ken Yun, Chris Myers, Rakefet Kol. "Apparatus and Method for Self-Timed Marking of Variable Length Instruction Having Length-Affecting Prefix Bytes''. Sept 7, 1999. United States Patent No. 5,948,096
• Ken Stevens, Shai Rotem, Ran Ginosar, Peter Beerel, Ken Yun, Chris Myers, Rakefet Kol. "Efficient Self-Timed Marking of Lengthy Variable Length Instructio ns''. 24 August 1999. United States Patent No. 5,941,982
• Ken Stevens, Shai Rotem, Ran Ginosar, Peter Beerel, Ken Yun, Chris Myers, Rakefet Kol. "Branch Instruction Handling in a Self-Timed Marking System''. August 3, 1999. United States Patent No. 5,931,944

High-Performance and Low-Power Designs:

• Design of a High-Speed Asynchronous Turbo Decoder, P. Golani, G. D. Dimou, M. Prakash, P. A. Beerel, 13th Symposium on Asynchronous Circuits ASYNC, Berkeley, CA, USA, March 2007.
• High Performance Asynchronous Design Using Single-Track Full-Buffer Standard Cells, M. Ferretti and P. A. Beerel, IEEE Journal of Solid-State Circuits, Vol. 41, No. 6, pp. 1444-1454, June 2006.
• High Performance Asynchronous ASIC Back-End Design Flow Using Single-Track Full-Buffer Standard Cells, M. Ferretti, R.O. Ozdag and P.A. Beerel, 10th Symposium on Asynchronous Circuits ASYNC, Herssonissos, Greece, April 2004.
• Efficient Asynchronous Bundled-Data Pipelines for DCT Matrix-Vector Multiplication, IEEE Transactions on VLSI Systems, vol. 3, no. 4., pp. 448-461, April 2005.
• A 0.18um implementation of a floating-point unit for a processing-in-memory system, T. Kwon, J.S. Moon, J. Sondeen, J. Draper Accepted for publication of ISCAS 2004.
• Voltage-pulse driven harmonic resonant rail drivers for low-power applications, J.S. Moon, W.C. Athas, S.D. Soli, J.T. Draper, P. A. Beerel IEEE Trans. VLSI Systems, Vol. 11, No. 5, Oct. 2003, pp762-777.
• An area-efficient standard-cell floating-point unit design for a processing-in-memory system, J.S. Moon, T. Kwon, J. Sondeen, J. Draper, European Solid-State Circuit Conference (ESSCIRC), Sep. 2003.
• An asynchronous pipeline comparisons with application to DCT matrix-vector multiplication, S. Tugsinavisut, S. Jirayucharoensak and P. A. Beerel, ISCAS'03, May. 2003.
• Asynchronous circuits: an increasingly practical design solution, P. A. Beerel, ISQED'02, pp. 367 -372, March. 2002.
• Low-Power Sequential Access Memory Design, J.S. Moon, W.C Athas, P.A. Beerel and J.T. Draper, CICC'02, May. 2002.
• High-Speed QDI Asynchronous Pipelines, R.O. Ozdag and P. A. Beerel, ASYNC'02, Apr. 2002.
• High-Speed Non-Linear Asynchronous Pipelines, R.O. Ozdag and P. A. Beerel, DATE'02, Mar. 2002.
• Single-Track Asynchronous Pipeline Templates using 1-OF-N Encoding , M. Ferretti and P. A. Beerel, DATE'02, Mar. 2002.
• Control Circuit Templates for Asynchronous Bundled-data Pipelines, S. Tugsinavisut and P. A. Beerel, DATE'02, Mar. 2002.
• Low Swing Signaling Using a Dynamic Diode-Connectedi Driver, M. Ferretti and P. A. Beerel, ESSCIRC'01, Sep. 2001.
• Theory and Practical Implementation of harmonic Resonant Rail Driver, J.S. Moon, W.C. Athas and P. A. Beerel, ISLPED'01, pp. 153-158, Aug. 2001.
• A Low Latency SISO with Application to Broadband Turbo Decoding, P. A. Beerel and K.M. Chugg, IEEE Journal on Selected Areas in Communications, Vol : 19 Issue: 5, May. 2001.
• An Asynchronous Instruction Length Decoder, K.S. Stevens, S. Rotem, R. Ginosar, P.A. Beerel, C.J. Myers, K.Y. Yun, R. Koi, C. Dike, M. Roncken, IEEE Journal of Solid-State Circuits, pp. 217-228, Feb. 2001.
• An /spl Oscr/(log/sub 2/N)-latency SISO with Application to Broadband Turbo Dec oding , P. A. Beerel and K.M. Chugg, MILCOM'00 Oct. 2000.
• An Asynchronous Matrix-Vector Multiplication for Discrete Cosine Transform, K. Kim, P. A. Beerel and Y. Hong, ISLPED'00, Jul. 2000.
• Algorithm and Circuit Co-design for a Low-Power Sequential Decoder, S.K. Singh, P. Thiennviboon, R.O. Ozdag, S. Tugsinavisut, P. A. Beerel and K.M. Chugg, ASILOMAR'99, pp. 389-394, Oct. 1999.
• MSB-Controlled Inversion Coding for Low-Power Matrix Transposer, K. Kim and P. A. Beerel, Accepted to IEE Electronic Letters, Aug. 1999.
• Statistically Optimized Asynchronous Barrel Shifters for Variable Length Codecs, P. A. Beerel, S. Kim, P.-C. Yeh, K. Kim. ISPLED'99, Aug. 1999.
• RAPPID: An Asynchronous Instruction Length Decoder, S. Rotem, K. Stevens, R. Ginosar, P. A. Beerel, C. Myers, K. Yun, R. Kol, C. Dike, M. Roncken, and B. Agapiev. ASYNC'99, April 1999.
• The Design and Verification of a Low-Control-Overhead Asynchronous Differential Equation Solver, K. Y. Yun, P. A. Beerel, V. Vakilotojar, A. Dooply, and J. Arceo. IEEE Transactions on VLSI, Dec. 1998.
• Speculative Completion for the Design of High-Performance Asynchronous Dynamic Adders, S. M. Nowick, K. Y. Yun, P. A. Beerel, and A. Dooply, ASYNC-97, April, 1997.
• The Design and Verification of a Low-Control-Overhead Asynchronous Differential Equation Solver, K. Y. Yun, P. A. Beerel, V. Vakilotojar, A. Dooply, and J. Arceo. ASYNC-97, April 1997.
• High-Performance Two-Phase Micropipeline Building Blocks: Double Edge-Triggered Latches and Burst-Mode Select and Toggle Circuits , K. Y. Yun, P. A. Beerel, and J. Arceo, In IEE Proceedings-Circuits, Devices and Systems. pp 282-288. Vol. 143, No. 5, October 1996.
• A Low-Control-Overhead Asynchronous Differential Equation Solver, K. Y. Yun, P. A. Beerel, V. Vakilotojar, A. Dooply, and J. Arceo, ESSCIRC-96, pp. 352-255. September, 1996.
• High-Performance Asynchronous Pipeline Circuits , K. Y. Yun, P. A. Beerel, and J. Arceo, ASYNC-96, pp 17-28. April, 1996.