Research Current Research Pages   Past Research Pages   Proteous: Asynchronous Logic Synthesis Approach and Static Timing Analysis SPHINX: Hierarchical Verification of Asynchronous Circuits LAST: Large-scale Asynchronous Synthesis Tool S-TSE Solver: A Performance Evaluation Tool for Stochastic Timed Petri Nets Asynchronous 1.45 GHz Prefix Tree Adder Technology mapping of asynchronous designs, AVEmap: Average-Case Optimized Technology Mapper RTCG Relative Timing Constraint Generator BDD minimization using don't cares. The source code for BDD minimization is available: compaction.tar Asynchronous Pipeline Comparisons Symbolic SCC identification and the Bad Cycle Detection Problem Our source code (consisting of two new VIS-1.3 directories) for identifying SCCs and bad cycles is now available: scc.tar If you have problems installing this code please contact pabeerel@usc.edu. VerilogCSP Macros added to Verilog for simulating CSP programs   Home | Publications | People | Research USC | Viterbi School of Engineering | EE Department The USC Asynchronous CAD/VLSI Group Hughes Aircraft Electrical Engineering Center EEB 100 Los Angeles, CA 90089-2560