RTCG: Relative Timing Constraints Generator

RTCG is a CAD tool for automatic generation of relative timing constraints for timed circuits and systems.

The tool is developed at the USC Asynchronous CAD/VLSI Group by Hoshik Kim as part of his PhD dissertation. Hoshik is a PhD candidate at the department of Electrical Engineering-Systems at the University of Southern California.

Many high performance circuit families today are timed circuits including synchronous and asynchronous self-resetting circuits. Agressive timed circuit families have demonstrated impressive performance gains at the cost of timing assumption. They are particularly challenging to design and verify due to complicated timing constraints that must hold to ensure correct operation. Identifying a small, sufficient and easily verifiable set of relative timing constraints simplifies both the design and verification.

While relative timing constraints can be derived manually relying on circuit designers' intuition, the process is timing-consuming and error-prone. This tool implements the first systematic algorithm to generate and optimize easily verifiable set of relative timing constraints sufficient to guarantee the correct operation of a circuit. The algorithms for both the generation and optimization of the constraints are based on the analysis of untimed state space which uses state-of-the-art symbolic reachability analysis techniques to handle large circuits and reduce run-time.

We provide a Solaris version of the tool for non-profit organizations with no guarantee or implied liability. You can download the distribution files for the source code and the example circuits using your web browser.

• Download the installation package for RTCG-1.0.0
  • The source code for RTCG requires that you first install glu-1.3. The distribution file on our web page includes the source code, benchmark circuits in the input file format and documentation files. This code has been tested and verified using cc and gcc compilers on SUN-OS 8. This distribution file also includes the installation packages for glu-1.3. You can download the latest version of the GLU packcage source code from VLSI/CAD Research Group at University of Colorado at Boulder's VIS Homepage.
• Download the RTCG User Documentation

For more information regarding the tool's technical background, we provide the following two papers:

• Relative Timing Based Verification of Timed Circuits and Systems, H. Kim, P.A. Beerel and K.S. Stevens. ASYNC'02, April 2002.
• Relative Timing Based Verification of Timed Circuits and Systems, H. Kim and P.A. Beerel. IWLS'99, June 1999. (PowerPoint presentation slides).

All questions or comments regarding this release of RTCG should only be directed to hoshik@usc.edu

This research has been partly supported by NSF grants ITR-0086036, CCR-9812164 and 53-4503-0640 and gifts from Intel, TRW and Fulcrum Microsystems.