• Mallika Prakash, Peter A. Beerel. “Static timing analysis of template-based asynchronous circuits,” United States Patent No. 8,972,915, March 3, 2015.
  • Georgios Dimou, Peter A. Beerel, Andrew Lines. "Multi-level domino, bundled data, and mixed templates," July 23, 2013, United States Patent No. 8,495,543.
  • Georgios Dimou, Peter A. Beerel, Andrew Lines. "Clustering and fanout optimizations of asynchronous circuits," May 21, 2013.  United States Patent No. 8,448,105.
  • Ken Shiring, Peter A. Beerel, Andrew Lines, and Arash Saifhashemi. "Power aware asynchronous circuits", Dec 27, 2011, United States Patent No. 8,086,975.
  • Peter Beerel, Andrew Lines, Michael Davies. "Logic synthesis of multi-level domino asynchronous pipelines," Nov 1, 2011: US Patent No. 8,051,396.
  • Peter A. Beerel, Keith M. Chugg, Georgios D. Dimou, Phunsak Thiennviboon. "Reduced-latency soft-input/soft-output module", March 27, 2007. United States Patent No. 7,197,691.

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