Blade - Bundled Data Resilient Design

Blade is a new asynchronous bundled-data resilient template that is robust to PVT variation, is metastability safe, requires no replay-based logic, and has low timing error penalties. It target is low-voltge low-power designs and IoT devices.

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SystemVerilogCSP is a SystemVerilog package for modeling channel-based digital asynchronous circuits.

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Past Research

Past resaerch project can be accessed here.



Proteus is a GHz Asynchronous ASIC Flow.

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