Blade - Bundled Data Resilient Design
Blade is a new asynchronous bundled-data resilient template that is robust to PVT variation, is metastability safe, requires no replay-based logic, and has low timing error penalties. It target is low-voltge low-power designs and IoT devices.
SystemVerilogCSP
SystemVerilogCSP is a SystemVerilog package for modeling channel-based digital asynchronous circuits.