Single-Track Full Buffer

This project introduced an ultra-high-performance asynchronous template based on single-track handshaking using commercial place-and-route tools for the physical design. A fabricated TSMC 0.25um chip technology demonstrated a ground-breaking 1.4GHz performance and opened the door for further commercialization of asynchronous design.


S-TSE Solver is a performance analysis tool for stochastic timed Petri nets (STPNs) with unique- and free-choice and general delay distributions. It is a refined version of what was called USC-PET.

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Symbolic SCC Identification

Our source code (consisting of two new VIS-1.3 directories) for identifying SCCs and bad cycles is now available: scc.tar. If you have problems installing this code please contact us.


LAST is an integrated computer-aided design tool for large-scale channel-based asynchronous architectures, providing a unifying high-level synthesis framework for multiple micro-architectural and circuit design styles.

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Average-Case Optimized Technology Mapper

AVEmap is a technology mapper for asynchronous burst-mode and one-hot domino circuits. The tool accepts un-mapped circuit implementations, a description of important input patterns with their probability, and a library description. It then creates a mapped circuit using library gates optimized for the average performance.

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SPHINX is a design verification tool for asynchronous circuits and systems which has the capability of verifying speed independence and conformance of asynchronous circuits to their specifications.

Read more: Sphinx

BDD Minimization using Don't Cares

The source code for BDD minimization is available:compaction.tar. See related publications here.

Asynchronous Pipeline Comparisons

The comprehensive energy-throughput comparisons of two well-known asynchronous design styles applied to a matrix-vector multiplication core of the discrete cosine transforms (DCTs) is presented.

Read more: Asynchronous Pipeline Comparisons