SystemVerilogCSP

SystemVerilogCSP is a SystemVerilog package for modeling channel-based digital asynchronous circuits.A SystemVerilog interface is used to model CSP-like communication events. The interfaces enable explicit handshaking of channel wires as well as abstract CSP events. This enables abstract connections between modules that are described at different levels of abstraction facilitating both verification and design.

Features:

• CSP-Like communication actions (Send/Receive)
• One-to-many (broadcast) channels
• Any-to-one channels
• Split communication

You can download this package from here and some examples can be found here.

Related paper: Arash Saifhashemi and Peter A. Beerel. SystemVerilogCSP:  Modeling Digital Asynchronous Circuits Using SystemVerilog Interfaces. CPA-2011: WoTUG-33, pages 287–302. IOS Press, 2011