Power and Performance Analysis and Optimization

Arash Saifhashemi, Hsin-Ho Huang, Peter A. Beerel: Reconditioning: Automatic Power Optimization of QDI Circuits. ASYNC 2014: 77-84. May 2014.
Arash Saifhashemi, Dylan Hand, Peter A. Beerel, William Koven, Hong Wang: Performance and Area Optimization of a Bundled-Data Intel Processor through Resynthesis. ASYNC 2014: 110-111, May 2014.
Mehrdad Najibi, Peter A. Beerel: Integrated Fanout Optimization and Slack Matching of Asynchronous Circuits. ASYNC 2014: 69-76, May 2014. (Best Paper Award Winner)
Slack Matching Mode-Based Asynchronous Circuits for Average-case Performance, Mehrdad Najibi and Peter A. Beerel, ICCAD 2013, Nov 18th-21st, 2013,
Deriving Performance Bounds for Conditional Asynchronous Circuits using Linear Programming, Mehrdad Najibi and Peter A. Beerel, 19th IEEE Symposium on Asynchronous Circuits ASYNC, Santa Monica, CA, May 19-22, 2013. (Best Paper Award Nominee)
Guowei Zhang, Peter A. Beerel: Stochastic analysis of Bubble Razor. DATE 2014: 1-6., March 2014.
Performance Bounds of Asynchronous Circuits with Mode-Based Conditional Behavior, Mehrdad Najibi and Peter A. Beerel, 18th Symposium on Asynchronous Circuits ASYNC, Copenhagen of Denmark, May 7-11, 2012.
Energy and Performance Models for Synchronous and Asynchronous Communication. Kenneth S. Stevens, Pankaj Golani, Peter A. Beerel. 2011, IEEE Trans. VLSI Syst., pp.369-382.
Timing Verification of GasP Asynchronous Circuits: Predicted Delay Variations Observed by Experiment, Prasad Joshi, Peter A. Beerel, Marly Roncken, and Ivan Sutherland, In D. Dams, U. Hannemann, M. Steffen (Eds.) Willem-Paul de Roever Festschrift, LNCS 5930, pages 260-276. Springer-Verlag Berlin Heidelberg, 2010.
Static Timing Analysis of Single Track Circuits, Prasad Joshi, Peter A. Beerel, Jonathan Gainsley, Ivan Sutherland, and Marly Roncken, DAC 2009 (User Track), June 2009.
Slack Matching Asynchronous Designs, P. A. Beerel, A. Lines, M. Davies, N.-H. Kim. in Proceedings of ASYNC’06, pp. 184-194, March 2006.
Crosstalk in High-Performance Asynchronous Designs. Ritej Bachhawat, Pankaj Golani and Peter A. Beerel. PATMOS 2009, pp.136~145. Sept. 2009.
Back-Annotation in High-Speed Asynchronous Design, (Invited) Journal of Low Power Electonics, Special Issue on PATMOS 2005, Pankaj Golani and Peter Beerel. American Scientific Publishers (ed), vol. 2, issue 2, pp. 37-44, April 2006.
Pipeline Optimization for Asynchronous Circuits: Complexity Analysis and an Efficient Optimal Algorithm, P. A. Beerel and S. Kim, IEEE Transactions on CAD, vol. 25, issue 3, pp 389-402, March 2006.
Reducing Probablilistic Timed Petri Nets for Asynchronous Architectural Analysis, S.Kim, S. Tugsinavisut, and P.A. Beerel, TAU'02, Dec. 2002.
Performance Analysis of Asynchronous Circuits Using Markov Chains. P. A. Beerel and A. Xie, In Concurrency and Hardware Design: Advances in Petri Nets, J. Cortadella, A. Yakovlev, G. Rozenberg (Eds), 2002.
Pipeline Optimization for Asynchronous Circuits: Complexity Analysis and an Efficient Optimal Algorithm , S. Kim and P. A. Beerel, ICCAD-2000, November 2000.
Implicit Enumeration of Strongly Connected Components and an Application to Formal Verification, A. Xie, P. A. Beerel, IEEE Transaction on CAD, Vol: 19 Issue: 10, Oct. 2000.
Implicit Enumeration of Strongly Connected Components , A. Xie, P. A. Beerel, ICCAD-99, November 1999.
Accelerating Markovian Analysis of Asynchronous Systems using State Compression , A. Xie, P. A. Beerel, IEEE Trans. on CAD, Vol. 18, No. 7, July 1999.
Performance Analysis of Asynchronous Circuits and Systems using Stochastic Timed Petri Nets, A. Xie, P. A. Beerel, (invited paper) the 2nd Internatio nal Workshop on Hardware Design and Petri Nets (HWPN-99), June 1999.
Bounding Average Time Separations of Events in Stochastic Timed Petri Nets with Choice, A. Xie, S. Kim, P. A. Beerel, ASYNC-99, April 1999. (Here is an extended version with proofs )
Efficient State Classification of Finite-State Markov Chains , A. Xie, P. A. Beerel, IEEE Trans. on CAD, Vol. 17, No. 12, December 1998.
Efficient State Classification of Finite-State Markov Chains , A. Xie, P. A. Beerel, DAC-98, June 1998.
Accelerating Markovian Analysis of Asynchronous Systems using String-based State C ompression , A. Xie, P. A. Beerel, ASYNC-98, April 1998.
Symbolic Techniques for Performance Analysis of Timed Circuits Based on Average Time Separation of Events , A. Xie, P. A. Beerel, ASYNC-97, April 1997.
Energy Estimation of Speed-Independent Control Circuits, P. A. Beerel, C.-T. Hsieh, S. Wadekar, IEEE Transactions on CAD, pp. 672-680. June, 1996.
Estimation and Bounding of Energy Consumption in Burst-Mode Control Circuits, P. A. Beerel, K. Y. Yun, S. M. Nowick, and P.-C. Yeh, ICCAD-95, Nov, 1995.