Low-Power, High-Performance and Resilient Designs

• Ramy N. Tadros, Nihar Dasari, and Peter. A. Beerel, “'Ultra-Low Power PTL-based Delay Line Design for Sub-threshold Application,” Accepted to Electronic Letters , Oct 2016.
• Ramy N. Tadros*, Weizhe Hua*, Matheus T. Moreira, Ney L. V. Calazans, and Peter A. Beerel. A Low Power, Low Area Error Detecting Latch for Resilient Architectures in 28nm FDSOI”, IEEE Transactions on Circuits and Systems II, vol. 63, no. 9, Sept. 2016.
• Weizhu Hua, Ramy N. Tadros, and Peter A. Beerel. A 2ps Resolution, Fine-Grained Delay Element in 28nm FDSOI”, Electronic Letters, vol. 51, no. 23, pp. 1848 – 1850, 2015.
• Peter A. Beerel and Ney L.V. Calazans, A Path Towards Average-Case Silicon via Asynchronous Resilient Bundled-data Design. 22nd European Conference on Circuit Theory and Design (ECCTD'15), (Invited) Aug. 2015
• Dylan Hand, Matheus T. Moreira, Hsin-Ho Huang, Danlei Chen, Fredericko Butzke, Zhichao Li, Matheus Gibiluka, Melvin Breuer, Ney. L.V. Calazans, Peter A. Beerel, Blade - A Timing Violation Resilient Asynchronous Template, ASYNC 2015, May 2015.
• Ajay Singhvi, Matheus T. Moreira, Ramy N. Tadros,  Peter A. Beerel, Ney L.V. Calazans, A Fine-Grained, Uniform, Energy-Efficient Delay Element for FD-SOI Technologies, International Symposium on VLSI (ISVLSI'15), July 2015.
• Matheus T. Moreira, Dylan Hand, Peter A. Beerel, Ney L.V. Calazans: TDTB error detecting latches: Timing violation sensitivity analysis and optimization. ISQED 2015: 379-383.
• Guiherme Heck, Leandro Heck, Ajay Singhvi, Matheus T. Moreira, Peter A. Beerel, Ney L.V. Calazans: Design and Analysis of Delay Elements for 2-Phase Bundled-Data Asynchronous Circuits, VLSI Design, Jan. 2015.
• Mike Davies, Andrew Lines, Jon Dama, Alain Gravel, Robert Southworth, Georgios D. Dimou, Peter A. Beerel: A 72-Port 10G Ethernet Switch/Router Using Quasi-Delay-Insensitive Asynchronous Design. ASYNC 2014: 103-104, May 2014.
• Pankaj Golani, Peter A. Beerel: Area-Efficient Asynchronous Multilevel Single-Track Pipeline Template. IEEE Trans. VLSI Syst. 22(4): 838-849, 2014
• Design of a High-Speed Asynchronous Turbo Decoder, P. Golani, G. D. Dimou, M. Prakash, P. A. Beerel, 13th Symposium on Asynchronous Circuits ASYNC, Berkeley, CA, USA, March 2007.
• High Performance Asynchronous Design Using Single-Track Full-Buffer Standard Cells, M. Ferretti and P. A. Beerel, IEEE Journal of Solid-State Circuits, Vol. 41, No. 6, pp. 1444-1454, June 2006.
• High Performance Asynchronous ASIC Back-End Design Flow Using Single-Track Full-Buffer Standard Cells, M. Ferretti, R.O. Ozdag and P.A. Beerel, 10th Symposium on Asynchronous Circuits ASYNC, Herssonissos, Greece, April 2004.
• Efficient Asynchronous Bundled-Data Pipelines for DCT Matrix-Vector Multiplication, IEEE Transactions on VLSI Systems, vol. 3, no. 4., pp. 448-461, April 2005.
• A 0.18um implementation of a floating-point unit for a processing-in-memory system, T. Kwon, J.S. Moon, J. Sondeen, J. Draper Accepted for publication of ISCAS 2004.
• Voltage-pulse driven harmonic resonant rail drivers for low-power applications, J.S. Moon, W.C. Athas, S.D. Soli, J.T. Draper, P. A. Beerel IEEE Trans. VLSI Systems, Vol. 11, No. 5, Oct. 2003, pp762-777.
• An area-efficient standard-cell floating-point unit design for a processing-in-memory system, J.S. Moon, T. Kwon, J. Sondeen, J. Draper, European Solid-State Circuit Conference (ESSCIRC), Sep. 2003.
• An asynchronous pipeline comparisons with application to DCT matrix-vector multiplication, S. Tugsinavisut, S. Jirayucharoensak and P. A. Beerel, ISCAS'03, May. 2003.
• Asynchronous circuits: an increasingly practical design solution, P. A. Beerel, ISQED'02, pp. 367 -372, March. 2002.
• Low-Power Sequential Access Memory Design, J.S. Moon, W.C Athas, P.A. Beerel and J.T. Draper, CICC'02, May. 2002.
• High-Speed QDI Asynchronous Pipelines, R.O. Ozdag and P. A. Beerel, ASYNC'02, Apr. 2002.
• High-Speed Non-Linear Asynchronous Pipelines, R.O. Ozdag and P. A. Beerel, DATE'02, Mar. 2002.
• Single-Track Asynchronous Pipeline Templates using 1-OF-N Encoding , M. Ferretti and P. A. Beerel, DATE'02, Mar. 2002.
• Control Circuit Templates for Asynchronous Bundled-data Pipelines, S. Tugsinavisut and P. A. Beerel, DATE'02, Mar. 2002.
• Low Swing Signaling Using a Dynamic Diode-Connectedi Driver, M. Ferretti and P. A. Beerel, ESSCIRC'01, Sep. 2001.
• Theory and Practical Implementation of harmonic Resonant Rail Driver, J.S. Moon, W.C. Athas and P. A. Beerel, ISLPED'01, pp. 153-158, Aug. 2001.
• A Low Latency SISO with Application to Broadband Turbo Decoding, P. A. Beerel and K.M. Chugg, IEEE Journal on Selected Areas in Communications, Vol : 19 Issue: 5, May. 2001.
• An Asynchronous Instruction Length Decoder, K.S. Stevens, S. Rotem, R. Ginosar, P.A. Beerel, C.J. Myers, K.Y. Yun, R. Koi, C. Dike, M. Roncken, IEEE Journal of Solid-State Circuits, pp. 217-228, Feb. 2001.
• An /spl Oscr/(log/sub 2/N)-latency SISO with Application to Broadband Turbo Dec oding , P. A. Beerel and K.M. Chugg, MILCOM'00 Oct. 2000.
• An Asynchronous Matrix-Vector Multiplication for Discrete Cosine Transform, K. Kim, P. A. Beerel and Y. Hong, ISLPED'00, Jul. 2000.
• Algorithm and Circuit Co-design for a Low-Power Sequential Decoder, S.K. Singh, P. Thiennviboon, R.O. Ozdag, S. Tugsinavisut, P. A. Beerel and K.M. Chugg, ASILOMAR'99, pp. 389-394, Oct. 1999.
• MSB-Controlled Inversion Coding for Low-Power Matrix Transposer, K. Kim and P. A. Beerel, Accepted to IEE Electronic Letters, Aug. 1999.
• Statistically Optimized Asynchronous Barrel Shifters for Variable Length Codecs, P. A. Beerel, S. Kim, P.-C. Yeh, K. Kim. ISPLED'99, Aug. 1999.
• RAPPID: An Asynchronous Instruction Length Decoder, S. Rotem, K. Stevens, R. Ginosar, P. A. Beerel, C. Myers, K. Yun, R. Kol, C. Dike, M. Roncken, and B. Agapiev. ASYNC'99, April 1999.
• The Design and Verification of a Low-Control-Overhead Asynchronous Differential Equation Solver, K. Y. Yun, P. A. Beerel, V. Vakilotojar, A. Dooply, and J. Arceo. IEEE Transactions on VLSI, Dec. 1998.
• Speculative Completion for the Design of High-Performance Asynchronous Dynamic Adders, S. M. Nowick, K. Y. Yun, P. A. Beerel, and A. Dooply, ASYNC-97, April, 1997.
• The Design and Verification of a Low-Control-Overhead Asynchronous Differential Equation Solver, K. Y. Yun, P. A. Beerel, V. Vakilotojar, A. Dooply, and J. Arceo. ASYNC-97, April 1997.
• High-Performance Two-Phase Micropipeline Building Blocks: Double Edge-Triggered Latches and Burst-Mode Select and Toggle Circuits , K. Y. Yun, P. A. Beerel, and J. Arceo, In IEE Proceedings-Circuits, Devices and Systems. pp 282-288. Vol. 143, No. 5, October 1996.
• A Low-Control-Overhead Asynchronous Differential Equation Solver, K. Y. Yun, P. A. Beerel, V. Vakilotojar, A. Dooply, and J. Arceo, ESSCIRC-96, pp. 352-255. September, 1996.
• High-Performance Asynchronous Pipeline Circuits , K. Y. Yun, P. A. Beerel, and J. Arceo, ASYNC-96, pp 17-28. April, 1996.